Memory devices are important components of many integrated circuits or electronic devices having integrated circuits. In a synchronous memory, data may be written to and read from the memory using a single clock signal. In an asynchronous memory, data may be written to and read from the memory using two separate asynchronous clocks. The asynchronous clocks not only have a different phase, but also have a different frequency. Memory devices also have various protocols for outputting stored data. For example, a first-in first-out (FIFO) memory is a memory device where a data sequence can be written to and retrieved from the memory in exactly the same order. Because no explicit addressing is required, the write and read operations of a FIFO can be completely independent of each other and use unrelated clocks. One common implementation of a FIFO is a random access memory (RAM) having two independently clocked ports (i.e. one for writing and one for reading), and two independent address counters to steer write and read data.
Because memories are so significant to the operation of integrated circuits and electronic devices in general, it is important that data stored in a memory device can be correctly loaded and/or accessed. In particular, FIFOs commonly include signals indicating certain conditions of the FIFO, such as “Almost Full” or “Almost Empty,” in order to avoid trying to load data in a FIFO which is full or read data from an empty FIFO. However, sometimes a strict specification of a system may limit options available to logic designers. One example of a system limit may be a maximum latency requirement. Although latency can be easily managed in a flow through design without any buffers, it becomes more complicated when a buffer, such as a FIFO, is introduced into the design. It may be particularly difficult to achieve the maximum throughput in a data path which contains both pipeline registers and a FIFO because of its latency requirement.
An example described in reference to FIG. 1 demonstrates the inefficiency which can result from a conventional design having pipeline registers and a FIFO limited by a latency requirement. In the circuit 100 of FIG. 1, a FIFO 102 is coupled to a pipeline stage 104 having a plurality of pipeline registers 106-112 for receiving user data in a data stream. Although the pipeline registers will be described as receiving data words of a data stream, by way of example, it should be understood that the data words could be single bit words, where the registers of the pipeline stage are single bit registers. A data valid stage 114 comprises a plurality of registers 116-122 for receiving data valid signals associated with the user data. The contents of the registers of the data valid stage indicate whether the data in a corresponding pipeline register is valid. That is, each register comprises a bit indicating whether the data in the corresponding pipeline register is valid. The output of the data valid stage 114 is coupled to a write enable port of the FIFO. Accordingly, when the data in the pipeline register 112 is valid (as indicated by a data bit “1” in the data valid register 122), data in the pipeline register is loaded into the FIFO on the next clock cycle.
In the conventional circuit shown in FIG. 1, the FIFO's Almost Full calculation always assumes the “worst case” scenario of a valid data word in each of the four pipeline registers. That is, because the loading of data from four pipeline registers into the FIFO cannot be stalled, the FIFO must always be able to accept four more data words after it asserts the Almost Full signal. In the example in this application where the FIFO has eight slots and four pipeline registers, the Almost Full signal is always asserted when words are present in four slots of the FIFO (regardless of the number of valid data words in the pipeline registers). Such a calculation is needed in the conventional circuit of FIG. 1 to ensure that data words in the pipeline registers will not cause the FIFO to overflow.
However, this calculation will prematurely trigger an Almost Full signal with only four words in the FIFO even when there are no valid data words in the pipeline registers, prompting the user to stop writing into the system, and therefore leading to inefficient operation of a system for processing data. This calculation adversely affects the system throughput, and particularly if the data transfer occurs in small bursts. As shown by way of example in FIG. 2, a burst of four data words (data words 1-4 loaded into the pipeline registers between times t1 and t5) will travel through the pipeline registers and be stored in the FIFO between times t5 and t9. After a time t5, when the first data word from the pipeline stage is loaded into the FIFO, the empty signal goes low. As can be seen, at time t9 when all four data words from the pipeline stage are read into the FIFO (which was previously empty), the Almost Full signal goes high, indicating that no new data should be read into the pipeline stage. That is, the FIFO will overflow if all of the pipeline registers have data and an additional data word is loaded into the pipeline stage when a word is written into the FIFO (already having words in four of the eight slots without reading one of the words from the FIFO). The Almost Full signal will remain asserted until a word is read out through the output interface of the FIFO.
When the read enable signal is high at time t11, data words are readout through the output interface. When there are less than four data words remaining in the FIFO as the data words are read out of the output interface, Almost Full signal will de-assert at time t12, indicating to the user of write interface to resume writing. However, before the very first data word of a second burst of data words (data words 5-8) can reach the FIFO from the pipeline registers, the empty flag is asserted because the FIFO has been emptied out by a user of the read interface. The empty signal will then trigger the read interface user to stop reading from the system. As can be seen, the empty flag is asserted between times t15 and t17, causing the read enable to go low between times t16 and t18. As a result, the output of data is delayed between times t16 and t19. Accordingly, the total throughput of the system is reduced because every Almost Full signal assertion is followed by an empty flag assertion causing the user of the read interface to stall its reading from the FIFO.
Accordingly, there is a need for a circuit and method of processing data input to FIFO having a pipeline stage to increase the throughput of the FIFO.